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layout synthesis造句

"layout synthesis"是什么意思   

例句与造句

  1. this dissertation advances that synthetic operation of engineering pipelines in a residential area is composed of two stages : layout synthesis and design synthesis, and the design synthesis is composed of outline design stage and shop drawing investigation stage
    本文提出了建筑小区工程管线综合工作阶段划分:建筑小区工程管线规划综合和建筑小区工程管线设计综合。其中设计综合又分为两个工作阶段:初步设计综合和施工图检查调整。
  2. similar with design verification problem, to predigest chip level layout synthesis problem, the layout synthesis based on the standard-cell methodology can be divided into two levels : inner standard-cell and among standard-cells . however, along with the increasing of chip size, chip level layout synthesis problem become more complex if it still bases on general manual standard-cell . because the router cannot impose the characteristic of the transistors in the standard-cell, it may reduce the performance of the whole chip
    通常,基于标准单元布图模式将版图综合划分成单元内与单元间两个层次,以简化芯片级自动版图综合问题的复杂性;但随着芯片规模的不断扩大,基于主要以手工定制的小规模标准单元,芯片级版图综合问题的复杂性不断增大,且标准单元间布线无法充分利用单元内晶体管特征,影响芯片的整体性能。
  3. similar with design verification problem, to predigest chip level layout synthesis problem, the layout synthesis based on the standard-cell methodology can be divided into two levels : inner standard-cell and among standard-cells . however, along with the increasing of chip size, chip level layout synthesis problem become more complex if it still bases on general manual standard-cell . because the router cannot impose the characteristic of the transistors in the standard-cell, it may reduce the performance of the whole chip
    通常,基于标准单元布图模式将版图综合划分成单元内与单元间两个层次,以简化芯片级自动版图综合问题的复杂性;但随着芯片规模的不断扩大,基于主要以手工定制的小规模标准单元,芯片级版图综合问题的复杂性不断增大,且标准单元间布线无法充分利用单元内晶体管特征,影响芯片的整体性能。
  4. similar with design verification problem, to predigest chip level layout synthesis problem, the layout synthesis based on the standard-cell methodology can be divided into two levels : inner standard-cell and among standard-cells . however, along with the increasing of chip size, chip level layout synthesis problem become more complex if it still bases on general manual standard-cell . because the router cannot impose the characteristic of the transistors in the standard-cell, it may reduce the performance of the whole chip
    通常,基于标准单元布图模式将版图综合划分成单元内与单元间两个层次,以简化芯片级自动版图综合问题的复杂性;但随着芯片规模的不断扩大,基于主要以手工定制的小规模标准单元,芯片级版图综合问题的复杂性不断增大,且标准单元间布线无法充分利用单元内晶体管特征,影响芯片的整体性能。
  5. It's difficult to find layout synthesis in a sentence. 用layout synthesis造句挺难的
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Last modified time:Thu, 14 Aug 2025 00:29:56 GMT